As semiconductors are miniaturized, in the next-generation lithography technique, extreme ultra-violet (EUV) light is used, which has a wavelength of 13.5 [nm] that is one digit shorter than ArF excimer laser light (wavelength: 193 [nm]) that is currently used for manufacturing a state-of-the-art device. Since absorption of light is increased as the wavelength becomes shorter and an aspect ratio of the resist pattern is made large and pattern collapse tends to occur because the width of the resist pattern is made very small in the generation using EUV lithography, the film thickness of a resist for EUV lithography is reduced. Specifically, an aspect ratio of about 3 or less with respect to the resist pattern width is set to a practical level. That is, in the case of EUV processing the resist film which is the uppermost layer of the stacked mask, the height of the resist film is about 30 [nm] in the generation with the pattern width of 10 [nm], and the height of the resist film is about 20 [nm] in the generation with the pattern width of 7 [nm].
In recent semiconductor devices, a finer pattern needs to be formed, so the influence of the fluctuation of the line pattern edge shape of the resist on device performance becomes obvious. The roughness of the line pattern edge shape is expressed using line width roughness (LWR: variation in a line width [nm]) and line edge roughness (LER: variation in a position of line edge [nm]) as indices. In a case where LER or LWR which is an index of variation in a mask shape increases, stabilization of a gate leakage current and a threshold voltage is hindered, the gate length is fluctuated, and each transistor performance in the LSI circuit varies.
In a semiconductor integrated circuit, on the same wafer, there are a dense pattern area having a large area density in which a memory, a logic portion, and the like are provided, and a sparse pattern area having a small area density in which a peripheral circuit portion and the like are provided. Therefore, in an etching step for manufacturing such a semiconductor integrated circuit, a control technique for realizing the accuracy of a desired pattern dimension formed by lithography is required, irrespective of the density of a pattern. Techniques related to pattern formation are disclosed in Patent Literatures 1 and 2.
An object of a plasma etching performance enhancing method described in Patent Literature 1 is to provide a method of forming a characteristic portion without bowing in a dielectric layer on a semiconductor wafer, by etching a structure defined by an etch mask using plasma. In the method described in Patent Literature 1, a mask is formed on a dielectric layer, protective silicon-containing coating is formed on an exposed surface of the mask, and the characteristic portion is etched through the mask and the protective silicon-containing coating. Further, in another method, the characteristic portion is partially etched prior to forming the protective silicon-containing coating. In this way, the technique described in Patent Literature 1 is to use plasma to form a protective silicon-containing coating on the resist mask and on the sidewall of the partially etched characteristic portion.
An object of a plasma etching method described in Patent Literature 2 is to provide a plasma etching method capable of suppressing variation in processing dimensions, in a plasma etching method by which plasma etching is performed using an EUV-exposed resist. The method described in Patent Literature 2 is a plasma etching method for plasma etching of a material to be etched, with a multilayer resist having an EUV-exposed resist, an antireflection film, an inorganic film, and an organic film as a mask, and the method includes a first step of depositing a deposited film on a surface of the resist before etching the antireflection film, a second step of etching the deposited film deposited on the antireflection film and the antireflection film using a mixed gas of Cl2 gas, HBr gas and N2 gas after the first step, a third step of etching the inorganic film after the second step, and a fourth step of etching the organic film after the third step. In this way, the technique of Patent Literature 2 is a technique capable of suppressing variation in processing dimensions using an EUV resist, in which a deposited film is deposited on a surface of a resist layer using plasma before etching a material to be etched.